The interface between 4H-SiC and SiO2 in metal oxide semiconductor field effect transistor (MOSFET) devices contains a high density of electrically active defects, which adversely affect the performance of SiC-based microelectronic devices by lowering the electron mobility. The electrical properties of these devices can be improved by a number of treatments, the most prevalent of which is a nitric oxide (NO) post-anneal. In addition to this, devices fabricated on different crystallographic faces of SiC, or with varying miscut at the interface show markedly different electronic performance. Our work on NO annealed devices has shown an inverse relationship between anneal time and the width of the transition layer at this interface, which is correlated with improved channel mobility, increased N interfacial density, and decreased charged interface trap density. We have performed a similar investigation on devices fabricated on various orientations (of the SiC substrate) and compared their interfacial qualities.
We present a characterization of the transition layer at the 4H-SiC/SiO2 interface in SiC MOSFET devices using high resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM), and spatially resolved electron energy-loss spectroscopy (EELS). In addition, we have characterized the effect of an NO post-anneal on interfacial states using X-ray photoemission spectroscopy (XPS), utilizing an improved chemical depth-profiling technique that will be described. Using the TEM techniques, we have investigated SiC/SiO2 interfaces fabricated on the Si-face, with and without miscut, as well as on the a-face. Transition layer information was obtained by chemical analysis through observation of the shift of the Si L2,3 EELS edge across the interface. Structural characterization of the interface was achieved by quantification of the interfacial roughness via HRTEM image observation and strain at the interface computed by geometric phase analysis (GPA). The results of these characterizations are discussed in terms of interface quality and its effect on device properties.
Our results demonstrate the importance of controlling the quality of the oxide-semiconductor interface in SiC power electronics and our methods provide a framework for analyzing devices processed under a range of various conditions.
*Supported by ARL under Grants No. W911NF-11-2-0044 and W911NF-07-2-0046, and NSF GRFP Grant No. DGE 1322106