For future high performance III-V n-channel MOS devices, In0.53Ga0.47As is a promising material for the channel due to its high electron mobility. Atomic layer deposited (ALD) Al2O3 has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs.1 Therefore, Al2O3 has received attention as either a candidate dielectric layer for InGaAs nMOSFETs, or as a large band-offset interface layer interposed between the InGaAs channel and a higher-k dielectric such as HfO2.2 Apart from the well-known oxide/InGaAs interface charge traps that may pin the Fermi level of the channel, traps in the oxide layer, called border traps, may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. In this presentation, we study the effects of various approaches to reduce the border trap density, such as variation of ALD temperature, post-gate metal forming gas (5% H2/95% N2) anneals (FGA). Experimental methods employed include quantitative interface trap and oxide trap modeling3, 4 of MOS capacitor data obtained over a range of frequencies and temperatures. With the application of these models, we find that MOS capacitors fabricated using trimethylaluminum (TMA)/H2O at an ALD temperature of 120ï¿½C have a considerably lower border trap density (Nbt) while maintaining a similarly low interface trap density (Dit) compared to samples prepared with a more standard 270ï¿½C Al2O3 ALD temperature. Large-dose TMA exposure (pre-dosing) of the InGaAs(100) surface prior to Al2O3 ALD is also found to be an important step to guarantee stable electrical quality of the low temperature-deposited samples. To understand the nature of this ALD temperature effect, composition and bonding characterization methods such as XPS and SIMS are employed to probe the origin of the Nbt variation as a function of the structure of the Al2O3 layer. Besides altering the ALD temperature, the impact of other treatment methods on the Nbt, such as variations of H2/N2 forming gas anneal time and temperature, and application of bias-temperature stress, will also be discussed. References 1. J. Ahn, T. Kent, E. Chagarov, K. Tang, A.C. Kummel, and P.C. McIntyre, Applied Physics Letters 103, 071602 (2013). 2. V. Chobpattana, T.E. Mates, W.J. Mitchell, J.Y. Zhang, and S. Stemmer, Journal of Applied Physics 114, 154108 (2013). 3. H. Chen, Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2383 (2012). 4. Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2100 (2012).