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2015 MRS Spring Meeting


CC11.07 - Improvement of Reliability by Inserting Un-Doped Poly-Si to Bottom of Floating Gate for Sub-20nm NAND Flash Memory


Apr 9, 2015 3:30pm ‐ Apr 9, 2015 3:45pm

Description

NAND flash memory technology has been scaled down continuously for more productivity, but at the same time reliability properties have become worse due to increase in trap generation in tunnel oxide and inter-poly dielectrics as well as cell-to-cell interference and disturbance. For the reliability enhancement, n-type poly Si floating gate (FG) has been replaced with p-type poly-Si. By adopting p-type poly-Si FG, the virgin threshold voltage increases and charge loss of programed cells in NAND flash memory devices decreases. Because p-type poly-Si FG may increase charge gain of erased cells, however, cautious approach is needed. Also, diffusion of boron atoms in the p-type poly-Si FG into tunnel oxide (Tox) makes Tox quality worse, leading to degradation of reliability properties. To simultaneously reduce the virgin Vth of cells and boron diffusion into Tox, a thin layer of un-doped poly-Si is inserted at the bottom of p-type poly-Si FG. We profile boron concentration using secondary ion mass spectroscopy(SIMS) and achieve the decreased boron concentration in Tox. To evaluate the improvement on reliability properties, electrical characteristics such as time dependent dielectric breakdown(TDDB), stress-induced leakage current(SILC), random telegraph noise(RTN), endurance and data retention have also been measured. The results indicate that inserting un-doped poly-Si produces lower trap density in Tox and better reliability as compared to the conventional process.

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